1. Field of the Invention
This invention is in the field of software tools for integrated circuit design and analysis.
2. Description of the Related Art
Modern integrated circuit chips are extremely complex devices, which may have millions of different electronic components (devices), such as NFET and PFETs, switches, and the like. These circuits, which are usually designed by teams of engineers using various circuit description languages (e.g. Berkeley SPICE, CDL (Circuit Description Language), Spectre™ LVS (Layout vs. Schematic) and the like). The circuits will typically comprise millions of individual devices and nets, and will often be powered by multiple power supplies (e.g. higher voltage, lower voltage, noisy, quiet, low current, higher current), as well. The chips are often so complicated that they far exceed the ability of the human designer's minds to fully understand, absent various computer assisted analytical tools.
Typically, integrated circuits are usually designed by using software tools to combine computer representations of various smaller blocks of circuits into computer representations of larger blocks of circuits, and then using other computer tools to connect the blocks through various Input/output (TO) interfaces and power connections. Each block has its own netlist and various devices, and these various smaller building blocks can be grouped into larger and larger circuit blocks, in a manner somewhat reminiscent of using image editors or CAD programs to construct final graphic images by combining various layers of sub-images.
Each block will generally have its own function, internal netlist, and power supply needs. As the various smaller or child blocks or sub-blocks are assembled into larger and larger parental blocks, the larger blocks can be viewed as created from a plurality of sub-blocks that are nested within the larger block. This block and nested sub-block type layered structure can often go on for many layers or nesting levels, until a final lowest “leaf” level is reached.
Thus the computer design tools used to design these chips typically store libraries of various standardized and debugged circuit blocks in memory. The various design engineers, during at least some phases of the circuit design process, select various blocks from design libraries. They then use their various computer design tools connect the various signal and power interfaces between these various blocks to form more complex designs.
For example, a large integrated circuit chip with perhaps 10 million devices or nets may have been built from 2000 circuit cells or larger assemblies of circuit blocks, many of which will be taken from the design library. As a result of this typical “pick circuit blocks from the library and place on the chip” type design process, the overall circuit netlist is organized as a series of blocks in a layered, branched, or nested hierarchy pattern. Some branches of this nested block hierarchy may be quite deep, while other branches may be quite shallow.
Thus at a high level, the overall circuit structure or netlist can be viewed as a being composed of major circuit domains, each with its own type of power supply. The various circuit domains in turn are composed of a hierarchy of nested blocks, with various signal and power interfaces between these various blocks.
Given the overall complexity of typical modern integrated circuits, it is inevitable that there will be many different types of design errors. Thus a large part of circuit design is focused on detecting and correcting these design errors.
Because different circuit blocks can have different power supply requirements, one common type of design error is an error where the power distribution scheme within a larger integrated circuit is inadequate to support the various power needs of the various circuit blocks and sub-blocks. Often this power distribution inadequacy may not be apparent at the highest level bocks, but rather is a problem that occurs lower in the hierarchy of nested lower level blocks.
Another type of power related design error is one in which the electrical signal interfaces or signal lines (TO interfaces) between different blocks with different power supplies are inadequate to cope problems caused by these different power supplies. For example, some blocks may be supplied by lower voltage power supplies, and their interfaces to other blocks, which may be supplied by higher voltage power supplies, must be adequately protected to properly convey the signal and to prevent circuit damage. As another example, some blocks may be supplied by noisy power supplies that with greater power fluctuations, their signal interfaces to other blocks, that are less tolerant to noise, and thus are served with lower noise power supplies, must also be adequate.
Although various computer analytical software tools, exemplified by the Cadence Spectre tool and the Synopsis HSIM tool, are available to trace various power related design flaws, such tools generally are focused a very detailed level of circuit design. As a result, such prior art tools fail to “see the forest for the trees” in that rather than reporting the root cause analysis of problems (e.g. the “crime suspect”), instead they tend to report on the huge number of “victims” instead. This tends to bury any important information in a sea of irrelevant results, and makes proper corrective action difficult.
Thus further improvements in computer software tools to detect and report high level problems in circuit design caused by inadequate power distribution schemes, and inadequate protection of signal interfaces from power related issues, would be useful.